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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33984 Rev 4.0, 09/2004
Advance Information Dual Intelligent High-Current Self-Protected Silicon High-Side Switch (4.0 m)
The 33984 is a dual self-protected 4.0 m silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33984 is designed for harsh environments, and it includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads.
33984
DUAL HIGH-SIDE SWITCH 4.0 m
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Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and pulse-width modulation (PWM) control of each output. SPI-programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33984 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs. Features * Dual 4.0 m Max High-Side Switch with Parallel Input or SPI Control * 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 A * Output Current Monitoring with Two SPI-Selectable Current Ratios * SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting * SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status * Enhanced -16 V Reverse Polarity VPWR Protection
Bottom View PNA SUFFIX SCALE 1:1 CASE 1402-02 16-TERMINAL PQFN (12 x 12)
ORDERING INFORMATION
Device MC33984PNA/R2 Temperature Range (TA) -40C to 125C Package 16 PQFN
Simplified Application Diagram 33984 Simplified Application Diagram
VDD
VDD
VDD 33984 VDD
VPWR VPWR GND
I/O I/O SO SCLK CS MCU SI I/O I/O I/O A/D
FS WAKE SI HS1 SCLK CS SO HS0 RST IN0 IN1 CSNS FSI GND
LOAD
LOAD
GND
This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2004
PWR GND
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VDD
VIC
VPWR
IUP
Internal Regulator
Overvoltage Protection
CS SO
SPI 3.0 MHz Programmable Switch Delay 0 ms -525 ms Selectable Slew Rate Gate Drive
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SI SCLK FS IN[0:1] RST WAKE
Selectable Overcurrent High Detection 100 A or 75 A Selectable Overcurrent Low Detection Blanking Time 0.15 ms-155 ms Selectable Overcurrent Low Detection 7.5 A -25 A Open Load Detection IDWN RDWN Overtemperature Detection
HS0
Logic
HS0
HS1
Programmable Watchdog 310 ms-2500 ms VIC IUP Selectable Output Current Recopy 1/20500 or 1/41000
HS1
FSI
GND
Figure 1. 33984 Simplified Internal Block Diagram
CSNS
33984 2
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Transparent Top View of Package
CSNS WAKE RST IN0 FS FSI CS SCLK SI VDD SO IN1 1 2 3 4 5 13 6 7 GND 8 9 10 11 12
16 14 VPWR
HS0
15
HS1
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TERMINAL DEFINITIONS Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 15.
Terminal 1 Terminal Name CSNS Formal Name Output Current Monitoring Definition This terminal is used to output a current proportional to the designated HS0-1 output. That current is fed into a ground-referenced resistor and its voltage is monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This terminal can be tri-stated through SPI. This terminal is used to input a logic [1] signal so as to enable the watchdog timer function. An internal clamp protects this terminal from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pulldown. This input terminal is used to initialize the device configuration and fault registers, as well as place the device in a low current sleep mode. The terminal also starts the watchdog timer when transitioning from logic LOW to logic HIGH. This terminal should not be allowed to be logic HIGH until VDD is in regulation. This terminal has a passive internal pulldown. This input terminal is used to directly control the output HS0. This input has an active internal pulldown current source and requires CMOS logic levels. This input may be configured via SPI. This is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. When a device fault condition is detected, this terminal is active LOW. Specific device diagnostic faults are reported via the SPI SO terminal. The value of the resistance connected between this terminal and ground determines the state of the outputs after a watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF, ON, or the output HSO only is ON. When the FSI terminal is connected to GND, the watchdog circuit and fail-safe operation are disabled. This terminal incorporates an active internal pullup current source. This input terminal is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS terminal of the selected device logic LOW, enabling SPI communication with the device. Other unselected devices on the serial link having their CS terminals pulled-up logic HIGH disregard the SPI communication data sent. This terminal incorporates an active internal pullup current source. This input terminal is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pulldown current source.
2
WAKE
Wake
3
RST
Reset (Active Low)
4
IN0
Serial Input
5
FS
Fault Status (Active Low)
6
FSI
Fail-Safe Input
7
CS
Chip Select (Active Low)
8
SCLK
Serial Clock
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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TERMINAL DEFINITIONS (continued) Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on page 15.
Terminal 9 Terminal Name SI Formal Name Serial Input Definition This is a command data input terminal connected to the SPI Serial Data Output of the MCU or to the SO terminal of the previous device of a daisy chain of devices. The input requires CMOS logic-level signals and incorporates an active internal pulldown current source. Device control is facilitated by the input's receiving the MSB first of a serial 8bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register. This is an external voltage input terminal used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. This output terminal is connected to the SPI Serial Data Input terminal of the MCU or to the SI terminal of the next device of a daisy chain of devices. This output will remain tri-stated (high impedance OFF condition) so long as the CS terminal of the device is logic HIGH. SO is only active when the CS terminal of the device is asserted logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. This input terminal is used to directly control the output HS1. This input has an active internal pulldown current source and requires CMOS logic levels. This input may be configured via SPI. This terminal is the ground for the logic and analog circuitry of the device. This terminal connects to the positive power supply and is the source input of operational power for the device. The VPWR terminal is a backside surface mount tab of the package. Protected 4.0 m high-side power output to the load. Protected 4.0 m high-side power output to the load.
10
VDD
Digital Drain Voltage (Power)
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11
SO
Serial Output
12
IN1
Serial Input
13 14
GND VPWR
Ground Positive Power Supply
15 16
HS1 HS0
High-Side Output 1 High-Side Output 0
33984 4
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit
ELECTRICAL RATINGS
Operating Voltage Range Steady-State VDD Supply Voltage Input/Output Voltage (Note 1) VDD VIN[0:1], RST, FSI CSNS, SI, SCLK,
CS, FS
VPWR -16 to 41 0 to 5.5 -0.3 to 7.0
V
V V
SO Output Voltage (Note 1)
VSO ICL(WAKE) ICL(CSNS) IHS[0:1] ECL[0:1] VESD1 VESD2
-0.3 to VDD +0.3 2.5 10 30 0.75
V mA mA A J V
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WAKE Input Clamp Current CSNS Input Clamp Current Output Current (Note 2) Output Clamp Energy (Note 3) ESD Voltage Human Body Model (Note 4) Machine Model (Note 5)
2000 200
THERMAL RATINGS
Operating Temperature Ambient Junction Storage Temperature Thermal Resistance (Note 6) Junction to Case Junction to Ambient Peak Terminal Reflow Temperature During Solder Mounting (Note 7) RJC RJA TSOLDER <1.0 20 230 TA TJ TSTG -40 to 125 -40 to 150 -55 to 150
C
C C/W
C
Notes 1. Exceeding voltage limits on RST, IN[0:1], or FSI terminals may cause a malfunction or permanent damage to the device. 2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150C). 4. 5. 6. 7. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). Device mounted on a 2s2p test board according to JEDEC JESD51-2. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER INPUT
Battery Supply Voltage Range Full Operational VPWR Operating Supply Current Output ON, IHS0 and IHS1 = 0 A VPWR Supply Current Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD, RST = VLOGIC HIGH Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V) TJ = 25C TJ = 85C VDD Supply Voltage VDD Supply Current No SPI Communication 3.0 MHz SPI Communication VDD Sleep State Current Overvoltage Shutdown Threshold Overvoltage Shutdown Hysteresis Undervoltage Output Shutdown Threshold (Note 8) Undervoltage Hysteresis (Note 9) Undervoltage Power-ON Reset IDD(SLEEP) VPWR(OV) VPWR(OVHYS) VPWR(UV) VPWR(UVHYS) VPWR(UVPOR) VDD(ON) IDD(ON) - - - 28 0.2 5.0 - - - - - 32 0.8 5.5 0.25 - 1.0 5.0 5.0 36 1.5 6.0 - 5.0 A V V V V V IPWR(SLEEP) - - 4.5 - - 5.0 10 50 5.5 V mA IPWR(SBY) - - 5.0 A IPWR(ON) - - 20 mA VPWR 6.0 - 27 mA V
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Notes 8. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 9. This applies when the undervoltage fault is not latched (IN[0:1] = 0).
33984 6
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT
Output Drain-to-Source ON Resistance (IHS[0:1] = 30 A, TJ = 25C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Drain-to-Source ON Resistance (IHS[0:1] = 30 A, TJ = 150C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Source-to-Drain ON Resistance IHS[0:1] = 15 A, TJ = 25C (Note 10) VPWR = -12 V Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 Overcurrent Low Detection Levels (SOCL[2:0]) 000 001 010 011 100 101 110 111 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 Current Sense Ratio (CSR0) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A -20 -14 -13 -12 -13 -13 - - - - - - 20 14 13 12 13 13 CSR0 CSR1 CSR0_ACC - - 1/20500 1/41000 - - % IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 21 18 16 14 12 10 8.0 6.0 25 22.5 20 17.5 15 12.5 10 7.5 29 27 24 21 17 15 12 9.0 - IOCH0 IOCH1 80 60 100 75 120 90 A RDS(ON) - - 8.0 A RDS(ON) - - - - - - 10.2 6.8 6.8 m RDS(ON) - - - - - - 6.0 4.0 4.0 m m
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Notes 10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT (continued)
Current Sense Ratio (CSR1) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A -25 -19 -18 -17 -18 -18 VCL(CSNS) 4.5 IOLDC VOLD(THRES) 2.0 VCL -20 TSD TSD(HYS) 160 5.0 - 175 - - 190 20 3.0 4.0 V 30 6.0 - 7.0 100 A V - - - - - - 25 19 18 17 18 18 V CSR1_ACC %
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Current Sense Clamp Voltage CSNS Open; IHS[0:1] = 29 A Open Load Detection Current (Note 11) Output Fault Detection Threshold Output Programmed OFF Output Negative Clamp Voltage 0.5 A < IHS[0:1] < 2.0 A, Output OFF Overtemperature Shutdown (Note 12) Overtemperature Shutdown Hysteresis (Note 12)
C C
Notes 11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 12. Guaranteed by process monitoring. Not production tested.
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
CONTROL INTERFACE
Input Logic High Voltage (Note 13) Input Logic Low Voltage (Note 13) Input Logic Voltage Hysteresis (Note 14) Input Logic Pulldown Current (SCLK, IN, SI)
RST Input Voltage Range
VIH VIL VIN[0:1](HYS) IDWN VRST CSO RDWN CIN VCL(WAKE)
0.7VDD - 100 5.0 4.5 - 100 -
- - 350 - 5.0 - 200 4.0
- 0.2VDD 750 20 5.5 20 400 12
V V mV A V pF k pF V
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SO, FS Tri-State Capacitance (Note 15) Input Logic Pulldown Resistor (RST) and WAKE Input Capacitance (Note 15) WAKE Input Clamp Voltage (Note 16) ICL(WAKE) < 2.5 mA WAKE Input Forward Voltage ICL(WAKE) = -2.5 mA SO High-State Output Voltage IOH = 1.0 mA
FS, SO Low-State Output Voltage
7.0 VF(WAKE) -2.0 VSOH 0.8 VDD VSOL - ISO(LEAK) -5.0 IUP 5.0 RFS RFSdis RFSoffoff RFSonoff RFSonon - 6.0 15 40
-
14 V
-
-0.3 V
-
- V
IOL = -1.6 mA SO Tri-State Leakage Current
CS > 0.7 VDD
0.2
0.4 A
0
5.0 A
Input Logic Pullup Current (Note 17)
CS, VIN[0:1] > 0.7 VDD
-
20 k
FSI Input Terminal External Pulldown Resistance FSI Disabled, HS[0:1] Indeterminate FSI Enabled, HS[0:1] OFF FSI Enabled, HS0 ON, HS1 OFF FSI Enabled, HS[0:1] ON
0 6.5 17 Infinite
1.0 7.0 19 -
Notes 13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage reference to VPWR. 14. Parameter is guaranteed by processing monitoring but is not production tested. 15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 16. The current must be limited by a series resistance when using voltages > 7.0 V. 17. Pullup current is with CS OPEN. CS has an active internal pullup to VDD.
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT TIMING
Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 18) 9.0 V < VPWR < 16 V Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 19) 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 18) 9.0 V < VPWR < 16 V SRRA_FAST 0.4 SRRB_FAST 0.03 SRFA_SLOW 0.2 SRFB_SLOW 0.03 SRFA_FAST 0.8 SRFB_FAST 0.1 t DLY(ON) 1.0 t DLY_SLOW(OFF) 20 t DLY_FAST(OFF) 10 f PWM - 60 300 200 - Hz 230 500 s 15 100 s 0.35 1.2 s 2.0 4.0 V/s 0.1 0.3 V/s 0.6 1.2 V/s 0.1 1.2 V/s 1.0 4.0 V/s SRRB_SLOW 0.03 0.1 0.3 V/s SRRA_SLOW 0.2 0.6 1.2 V/s V/s
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Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 19) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 18) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 19) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 18) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 19) 9.0 V < VPWR < 16 V Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 20) DICR = 0, DICR = 1 Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 21) DICR = 0 Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 21) DICR = 1 Direct Input Switching Frequency (DICR D3 = 0)
Notes 18. Rise and Fall Slew Rates A measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR -3.5 V. These parameters are guaranteed by process monitoring. 19. Rise and Fall Slew Rates B measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR -3.5 V. These parameters are guaranteed by process monitoring. 20. Turn-ON delay time measured from rising edge of IN[0:1] signal that would turn the output ON to VHS[0:1] = 0.5 V with RL = 5.0 resistive load. 21. Turn-OFF delay time measured from falling edge that would turn the output OFF to VHS[0:1] = VPWR -0.5 V with RL = 5.0 resistive load.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT TIMING (continued)
Overcurrent Detection Blanking Time (OCLT[1:0]) 00 01 10 11 Overcurrent High Detection Blanking Time
CS to CSNS Valid Time (Note 22)
ms
t OCL0 t OCL1 t OCL2 t OCL3 t OCH t CNSVAL t OSD0 t OSD1 t OSD2 t OSD3 t OSD4 t OSD5 t OSD6 t OSD7 t OSD0 t OSD1 t OSD2 t OSD3 t OSD4 t OSD5 t OSD6 t OSD7 t WDTO0 t WDTO1 t WDTO2 t WDTO3
108 7.0 0.8 0.08 1.0 -
155 10 1.2 0.15 10 -
202 13 1.6 0.25 20 10 s s ms
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HS0 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 HS1 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 Watchdog Timeout (WD[1:0]) (Note 23) 00 01 10 11 434 207 1750 875 620 310 2500 1250 806 403 3250 1625 - - 110 110 220 220 330 330 0 0 150 150 300 300 450 450 - - 190 190 380 380 570 570 - 55 110 165 220 275 330 385 0 75 150 225 300 375 450 525 - 95 190 285 380 475 570 665
ms
ms
Notes 22. Time necessary for the CSNS to be within 5% of the targeted value. 23. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation Required Low State Duration for RST (Note 24) Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 25) Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 25) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 25) f SPI - - - - - - - - - - - 50 - - 50 - - 50 25 25 3.0 350 300 5.0 167 167 167 167 83 83 MHz ns ns s ns ns ns ns ns ns ns - 25 50 ns - 25 - - - 65 50 50 50 145 145 ns ns ns ns ns - 65 105
t WRST
t CS
t ENBL t LEAD t WSCLKh t WSCLKl t LAG t SI(SU) t SI(HOLD) t RSO t FSO t RSI t RSI t SO(EN) t SO(DIS) t VALID
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Required High State Duration of SCLK (Required Setup Time) (Note 25) Required Low State Duration of SCLK (Required Setup Time) (Note 25) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 25) SI to Falling Edge of SCLK (Required Setup Time) (Note 26) Falling Edge of SCLK to SI (Required Setup Time) (Note 26) SO Rise Time CL = 200 pF SO Fall Time CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (Note 26) SI, CS, SCLK, Incoming Signal Fall Time (Note 26) Time from Falling Edge of CS to SO Low Impedance (Note 27) Time from Rising Edge of CS to SO High Impedance (Note 28) Time from Rising Edge of SCLK to SO Data Valid (Note 29) 0.2 VDD SO 0.8 VDD, CL = 200 pF Notes 24. 25. 26. 27. 28. 29.
- - - -
RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 k on pullup on CS. Time required for output status data to be terminated at SO. 1.0 k on pullup on CS. Time required to obtain valid data out from SO following the rise of SCLK.
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Timing Diagrams
CS
VPWR VPWR - 0.5V VVPWR-0.5 V PWR VPWR - 3V VPWR -3.5 V
SRRB SRrB
SRFB SRfB SRFA SRfA
SRRA SRrA
0.5V 0.5
V t DLY(OFF) Tdly(off)
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t DLY(ON) Tdly(on)
Figure 2. Output Slew Rate and Time Delays
IOCHx ILOAD1 ILOAD1 IOCLx t OCH Time t OCLx Figure 3. Overcurrent Shutdown
Load Current
IOCH0 IOCH1 IOCL0
IOCL1
Load Current
IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7
Time
t OCHx t OCL3 t OCL2 t OCL1 t OCL0
Figure 4. Overcurrent Low and High Detection
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VIH V
IH
RSTB RST
0.2 VDD 0.2 VDD
TwRSTB
VIL TCSB t CS
VIL
t WRST
t ENBL
TENBL
0.7 VDD 0.7VDD CS CSB 0.7 VDD 0.7VDD tTlead LEAD t WSCLKh TwSCLKh t RSI
TrSI
VIH V
IH
VIL V
IL
SCLK SCLK
0.7 VDD 0.7VDD 0.2 VDD
0.2VDD
t LAG Tlag
VIH VIH VIL V
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t TSIsu SI(SU)
t WSCLKl TwSCLKl
IL
t SI(HOLD) TSI(hold)
TfSI t FSI VIH V
IH
SI SI
Don't Care
0.7 VDD 0.7 VDD 0.2VDD 0.2 VDD
Valid
Don't Care
Valid
Don't Care
VIH VIL
Figure 5. Input Timing Switching Characteristics
t RSI
t FSI
TrSI
3.5 3.5V V
TfSI VOH VOH 50% 1.0V 1.0 V VOL VOL
SCLK SCLK
t SO(EN)
TdlyLH
SO SO
0.7 VDD VDD
VOH VOH VOL VOL
0.2 VDD 0.2 VDD TrSO t RSO TVALID t VALID
Low-to-High Low to High
SO
SO
0.7 VDD High to Low High-to-Low 0.7 VDD
TfSO t FSO
VOH VOH
TdlyHL
t SO(DIS)
0.2VDD 0.2 VDD
VOL VOL
Figure 6. SCLK Waveform and Valid SO Data Delay Time
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33984 is a dual self-protected 4.0 m silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33984 is designed for harsh environments, and it includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and Pulse Width Modulation (PWM) control of each output. SPI-programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33984 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs.
FUNCTIONAL DESCRIPTION
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SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI/SO terminals of the 33984 follow a first-in first-out (D7/D0) protocol with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI lines perform the following functions: Serial Clock (SCLK) Serial clocks (SCLK) the internal shift registers of the 33984 device. The serial input (SI) terminal accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) terminal shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK terminal be in a logic low state whenever CS makes any transition. For this reason, it is recommended that the SCLK terminal be in a logic [0] state whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pulldown, IDWN. When CS is logic [1], signals at the SCLK and SI terminals are ignored and SO is tri-stated (high impedance). (See Figure 7 and Figure 8 on page 16.) Serial Input (SI) This is a serial interface (SI) command data input terminal. SI instruction is read on the falling edge of SCLK. An 8-bit stream of serial data is required on the SI terminal, starting with D7 to
D0. The internal registers of the 33984 are configured and controlled using a 4-bit addressing scheme, as shown in Table 1, page 16. Register addressing and configuration are described in Table 2, page 17. The SI input has an active internal pulldown, IDWN. Serial Output (SO) The SO data terminal is a tri-stateable output from the shift register. The SO terminal remains in a high impedance state until the CS terminal is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO terminal changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and Input Status descriptions are provided in Table 11, page 21. Chip Select (CS) The CS terminal enables communication with the master microcontroller (MCU). When this terminal is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 33984 device latches in data from the Input shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pullup, IUP.
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CSB CS SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
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Notes NOTES: 1. 2. 3.
1. RST is a logic1 state during the above operation. RST RSTB is in a logic [1] state during the above operation. 2. D7:D0 relate to the most the mostordered entry entry of data into the SPSS D0, D1, D2, ..., and D7 relate to recent recent ordered of data into the device. OD0, OD1, OD2, ..., and the relate bits first 8 bits of ordered fault and data data out 3. OD7:OD0 relate to OD7 first 8 to theof ordered fault and status status out of the device.
of the device.
Figure 7. Single 8-Bit Word SPI Communication
CSB CS
SCLK SCLK
S SI I
D7
D6
D5
D2
D1
D0
D 7*
D 6*
D 5*
D 2*
D1*
D0*
SO SO
OD7
OD6
OD5
OD2
OD1
OD0
D7
D6
D5
D2
D1
D0
R a logic [1] 1. R B lo g i 1 s ta t d u in g t h above op NOT : NotesE S1. RST is SST,T D 1 i ,s Di n2 ,astatec duringr eethe eraboveeoperation. e rt aot ir od ne .r e d e n t r y o f d a t a i n t o t h e S P S S 2. D0 ..., a n d D 7 la t to th e m o s t re c e n 3. O D 0 , O to O 2 , . . . a n d O ordered t o t h f s t 8 into f o d e r e d f 2. D7:D0 relate D 1 ,theDmost, recent D 7 r e l a t e entry eofi rdata b i t s othe r device.a u l t a n d s t a t u s d a t a o u t o f t h e d e v i c e . 4. O D 0 , O D 1 , O D 2 , .. ., a n d O D 7 r e p r e s e n t t h e f ir s t 8 b its o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e S P S S 3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device. 4. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
F IG U R E
4b.
M U L T IP L E
8 b it W O R D
S P I C O M M U N IC A T IO N
Figure 8. Multiple 8-Bit Word SPI Communication
Serial Input Communication
SPI communication is accomplished using 8-bit messages. A message is transmitted by the MCU starting with the MSB, D7, and ending with the LSB, D0 (Table 1). Each incoming command message on the SI terminal can be interpreted using the following bit assignments: the MSB (D7) is the watchdog bit and in some cases a register address bit common to both outputs or specific to an output; the next three bits, D6:D4, are used to select the command register; and the remaining four bits, D3:D0, are used to configure and control the outputs and their protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of eight bits. Any attempt made to latch in a message that is not eight bits will be ignored. The 33984 has defined registers, which are used to configure the device and to control the state of the output. Table 2 page 17, summarizes the SI registers. The registers are addressed via D6:D4 of the incoming SPI word (Table 1).
Bit Sig
Table 1. SI Message Bit Assignment
SI Msg Bit Message Bit Description
MSB
D7
Register address bit for output selection. Also used for Watchdog: toggled to satisfy watchdog requirements. Register address bits. Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content.
D6:D4 D3:D1
LSB
D0
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Address x010-- Select Overcurrent High and Low Register (SOCHLR) The SOCHLR register allows the MCU to configure the output overcurrent low and high detection levels, respectively. Each output is independently selected for configuration based on the state of the D7 bit; a write to this register when D7 is logic [0] will configure the current detection levels for the HS0. Similarly, if D7 is logic [1] when this register is written, HS1 is configured. Each output can be configured to different levels. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements matching system characteristics. Bits D2:D0 set the overcurrent low detection level to one of eight possible levels, as shown in Table 3. Bit D3 sets the overcurrent high detection level to one of two levels, which is described in Table 4. Table 3. Overcurrent Low Detection Levels
SOCL2 (D2) SOCL1 (D1) SOCL0 (D0) Overcurrent Low Detection (Amperes)
Table 2. Serial Input Address and Configuration Bit Map
SI Register D7 D6 D5 D4 Serial Input Data D3 D2 D1 D0
STATR OCR SOCHLR CDTOLR DICR OSDR
SO A3 x s s s 0 1 0 1 x
0 0 0 0 1 1 1 1 1 1
0 0 1 1 0 0 0 1 1 1
0 1 0
0 CSNS1
EN
SOA2 IN1_SPI SOCL2s
SOA1 CSNS0
EN
SOA0 IN0_SPI SOCL0s OCLT0s A/Os OSD0 WD0 0 OV_dis
SOCHs
SOCL1s OCLT1s IN DIS s OSD1 WD1 0 UV_dis
1 OL DIS s CD DIS s 0 1 1 0 0 1 FAST SR s 0 0 0 0 CSNS high s OSD2 0 0 0
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WDR NAR UOVR TEST
Motorola Internal Use (Test)
0 0 0 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
25 22.5 20 17.5 15 12.5 10 7.5
x = Don't care. s = Selection of output: logic [0] = HS0, logic [1] = HS1.
Device Register Addressing
The following section describes the possible register addresses and their impact on device operation. Address x000--Status Register (STATR) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D2:D0, determine the content of the first eight bits of SO data. When register content is specific to one of the two outputs, bit D7 is used to select the desired output. In addition to the device status, this feature provides the ability to read the content of the OCR, SOCHLR, CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers. (Refer to the section entitled Serial Output Communication (Device Status Return Data) beginning on page 19.) Address x001--Output Control Register (OCR) The OCR register allows the MCU to control the outputs through the SPI. Incoming message bit D0 reflects the desired states of the high-side output HS0 (IN0_SPI): a logic [1] enables the output switch and a logic [0] turns it OFF. A logic [1] on message bit D1 enables the Current Sense (CSNS) terminal. Similarly, incoming message bit D2 reflects the desired states of the high-side output HS1 (IN1_SPI): logic [1] enables the output switch and a logic [0] turns it OFF. A logic [1] on message bit D3 enables the CSNS terminal. In the event that the current sense is enabled for both outputs, the current will be summed. Bit D7 is used to feed the watchdog if enabled.
1 1 1 1
Table 4. Overcurrent High Detection Levels
SOCH (D3) Overcurrent High Detection (Amperes)
0 1
100 75
Address x011--Current Detection Time and Open Load Register (CDTOLR) The CDTOLR register is used by the MCU to determine the amount of time the device will allow an overcurrent low condition before output latches OFF occurs. Each output is independently selected for configuration based on the state of the D7 bit. A write to this register when bit 7 is logic [0] will configure the timeout for the HS0. Similarly, if D7 is logic [1] when this register is written, then HS1 is configured. Bits D1:D0 allow the MCU to select one of four fault blanking times defined in Table 5, page 18. Note that these timeouts apply only to the overcurrent low detection levels. If the selected overcurrent high level is reached, the device will latch off within 20 s.
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A write to this register configures both outputs for different delay. Whenever the input is commanded to transition from logic [0] to logic [1], both outputs will be held OFF for the time delay configured in the OSDR. The programming of the contents of this register have no effect on device fail-safe mode operation. The default value of the OSDR register is 000, equating to no delay. This feature allows the user a way to minimize inrush currents, or surges, thereby allowing loads to be switched ON with a single command. There are eight selectable output switching delay times that range from 0 ms to 525 ms (refer to Table 6). Table 6. Switching Delay
OSD[2:0] (D2:D0) Turn ON Delay (ms) HS0 Turn ON Delay (ms) HS1
Table 5. Overcurrent Low Detection Blanking Time
OCLT[1:0] Timing
00 01 10 11
155 ms 10 ms 1.2 ms 150 s
A logic [1] on bit D2 disables the overcurrent low (CD dis) detection timeout feature. A logic [1] on bit D3 disables the open load (OL) detection feature. Address x100--Direct Input Control Register (DICR)
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The DICR register is used by the MCU to enable, disable, or configure the direct IN terminal control of each output. Each output is independently selected for configuration based on the state of bit D7. A write to this register when bit D7 is logic [0] will configure the direct input control for the HS0. Similarly, if D7 is logic [1] when this register is written, then HS1 is configured. A logic [0] on bit D1 will enable the output for direct control by the IN terminal. A logic [1] on bit D1 will disable the output from direct control. While addressing this register, if the input was enabled for direct control, a logic [1] for the D0 bit will result in a Boolean AND of the IN terminal with its corresponding D0 message bit when addressing the OCR register. Similarly, a logic [0] on the D0 terminal results in a Boolean OR of the IN terminal with the corresponding message bits when addressing the OCR register. The DICR register is useful if there is a need to independently turn on and off several loads that are PWM'd at the same frequency and duty cycle with only one PWM signal. This type of operation can be accomplished by connecting the pertinent direct IN terminals of several devices to a PWM output port from the MCU and configuring each of the outputs to be controlled via their respective direct IN terminal. The DICR is then used to Boolean AND the direct IN(s) of each of the outputs with the dedicated SPI bit that also controls the output. Each configured SPI bit can now be used to enable and disable the common PWM signal from controlling its assigned output. A logic [1] on bit D2 is used to select the high ratio (CSR1, 1/41000) on the CSNS terminal for the selected output. The default value [0] is used to select the low ratio (CSR0, 1/20500). A logic [1] on bit D3 is used to select the high speed slew rate for the selected output. The default value [0] corresponds to the low speed slew rate. Address 0101--Output Switching Delay Register (OSDR) The OSDR register configures the device with a programmable time delay that is active during Output ON transitions initiated via SPI (not via direct input).
000 001 010 011 100 101 110 111
0 75 150 225 300 375 450 525
0 0 150 150 300 300 450 450
Address 1101--Watchdog Register (WDR) The WDR register is used by the MCU to configure the watchdog timeout. Watchdog timeout is configured using bits D1:D0. When D1:D0 bits are programmed for the desired watchdog timeout period, the WD bit (D7) should be toggled as well, ensuring the new timeout period is programmed at the beginning of a new count sequence (refer to Table 7). Table 7. Watchdog Timeout
WD[1:0] (D1:D0) Timing (ms)
00 01 10 11
620 310 2500 1250
Address 0110--No Action Register (NAR) The NAR register can be used to no-operation fill SPI data packets in a daisy chain SPI configuration. This allows devices to not be affected by commands being clocked over a daisychained SPI configuration, and by toggling the WD bit (D7), the watchdog circuitry will continue to be reset while no programming or data readback functions are being requested from the device.
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Address 1110--Undervoltage/Overvoltage Register (UOVR) The UOVR register can be used to disable or enable overvoltage and/or undervoltage protection. By default (logic [0]), both protections are active. When disabled, an undervoltage or overvoltage condition fault will not be reported in the output fault register. Address x111--TEST The TEST register is reserved for test and is not accessible with SPI during normal operation. message length is a multiple of eight bits. At this time, the SO terminal is tri-stated and the fault status register is now able to accept new fault status information. The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a logic [0] during SPI communication and/or for the period of time since the last valid SPI communication, with the following exceptions: * The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. * Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored. * The RST terminal transition from a logic [0] to logic [1] while the WAKE terminal is at logic [0] may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored.
Serial Output Communication (Device Status Return Data)
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When the CS terminal is pulled low, the output status register is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first as the new message data is clocked into the SI terminal. The first eight bits of data clocking out of the SO, and following a CS transition, are dependant upon the previously written SPI word. Any bits clocked out of the SO terminal after the first eight will be representative of the initial message bits clocked into the SI terminal since the CS terminal first transitioned to a logic [0]. This feature is useful for daisy chaining devices as well as message verification. A valid message length is determined following a CS transition of logic [0] to logic [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid
Serial Output Bit Assignment
The 8 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 8 summarizes the SO register content.
Table 8. Serial Output Bit Map Description
Previous STATR D7, D2, D1, D0 SOA3 SOA2 SOA1 SOA0 OD7 OD6 OD5 Serial Output Returned Data OD4 OD3 OD2 OD1 OD0
s x s s s 0 1 0 1 x
0 0 0 0 1 1 1 1 1 1
0 0 1 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0 0 1
s x s s s 0 1 0 1 -
OTFs 0 0 0 1 1 1 1 1 -
OCHFs 0 1 1 0 0 0 1 1 -
OCLFs 1 0 1 0 1 1 0 0 -
OLFs CSNS1 EN SOCHs OL DIS s FAST SR s FSM_HS0 FSM_HS1
UVF IN1_SPI SOCL2s CD DIS s CSNS high s OSD2 WDTO
OVF CSNS0 EN SOCL1s OCLT1s IN DIS s OSD1 WD1
FAULTs IN0_SPI SOCL0s OCLT0s A/Os OSD0 WD0 WAKE Terminal OV_dis -
IN1 Terminal IN0 Terminal FSI Terminal - - - - UV_dis -
s = Selection of output: logic [0] = HS0, logic [1] = HS1. x = Don't care.
Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The value of the previous D7 will determine which output the status information applies to for the Fault (FLTR), SOCHLR, CDTOLR, and DICR registers. SO data will represent information ranging from fault status to
register contents, user selected by writing to the STATR bits D2:D0. Note that the SO data will continue to reflect the information for each output (depending on the previous D7 state) that was selected during the most recent STATR write until changed with an updated STATR write.
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Previous Address SOA[2:0]=000 If the previous three MSBs are 000, bits OD6:OD0 will reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bit OD7 (Table 9). Table 9. Fault Register
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Previous Address SOA[2:0]=100 The returned data contain the programmed values in the DICR. Previous Address SOA[2:0]=101 * SOA3 = 0. The returned data contain the programmed values in the OSDR. Bit OD3 (FSM_HS0) reflects the state of the output HS0 in the Fail-Safe mode after a watchdog timeout occurs. * SOA3 = 1. The returned data contain the programmed values in the WDR. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is logic [1], the watchdog has timed out and the device is in Fail-Safe mode. If WDTO is logic [0], the device is in Normal mode (assuming the device is powered and not in Sleep mode), with the watchdog either enabled or disabled. Bit OD3 (FSM_HS1) reflects the state of the output HS1 in the FailSafe mode after a watchdog timeout occurs. Previous Address SOA[2:0] =110 * SOA3 = 0. OD3:OD0 return the state of the IN1, IN0, FSI, and WAKE terminals, respectively (Table 10). Table 10. Terminal Register
OD3 OD2 OD1 OD0
s
OTF
OCHFs OCLFs
OLFs
UVF
OVF
FAULTs
OD7 (s) = Selection of output: logic [0] = HS0, logic [1] = HS1. OD6 (OTF) = Overtemperature Flag. OD5 (OCHFs) = Overcurrent High Flag. (This fault is latched.) OD4 (OCLFs) = Overcurrent Low Flag. (This fault is latched.) OD3 (OLFs) = Open Load Flag.
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OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.) OD1 (OVF) = Overvoltage Flag. OD0 (FAULTs) = This flag reports a fault and is reset by a read operation.
Note The FS terminal reports a fault. For latched faults, this terminal is reset by a new Switch ON command (via SPI or direct input IN).
Previous Address SOA[2:0]=001 Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI programmed bits, respectively. Data in bits OD3:OD2 contain CSNS0 EN and IN0_SPI programmed bits, respectively. Previous Address SOA[2:0]=010 The data in bit OD3 contain the programmed overcurrent high detection level (refer to Table 4, page 17), and the data in bits OD2:OD0 contain the programmed overcurrent low detection levels (refer to Table 3, page 17). Previous Address SOA[2:0]=011 Data returned in bits OD1 and OD0 are current values for the overcurrent fault blanking time, illustrated in Table 5, page 18. Bit OD2 reports if the overcurrent detection timeout feature is active. OD3 reports if the open load circuitry is active.
IN1 Terminal
IN0 Terminal
FSI Terminal
WAKE Terminal
* SOA3 = 1. The returned data contain the programmed values in the UOVR. Bit OD1 reflects the state of the undervoltage protection and bit OD0 reflects the state of the overvoltage protection (refer to Table 8, page 19). Previous Address SOA[2:0]=111 Null Data. No previous register Read Back command received, so bits OD2:OD0 are null, or 000.
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MODES OF OPERATION
The 33984 has four operating modes: Sleep, Normal, Fault, and Fail-Safe. Table 11 summarizes details contained in succeeding paragraphs. Table 11. Fail-Safe Operation and Transitions to Other 33984 Modes
Mode
FS
Fail-Safe Mode
Fail-Safe Mode and Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input terminal transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance that limits the internal clamp current according to the specification. The watchdog timeout is a multiple of an internal oscillator and is specified in Table 7, page 18. As long as the WD bit (D7) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized. During the Fail-Safe mode, the outputs will be ON or OFF depending upon the resistor RFS connected to the FSI terminal, regardless of the state of the various direct inputs and modes (Table 12). In this mode, the SPI register content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, and OCLT). Then the watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value) are fully operational. Table 12. Output State During Fail-Safe Mode
RFS (k) High-Side State
WAKE
RST
WDTO
Comments
Sleep Normal
x 1 0
0 x 1 x 0 1 1
0 1 x 1 1 1 0
x No
Device is in Sleep mode. All outputs are OFF. Normal mode. Watchdog is active if enabled. The device is currently in Fault mode. The faulted output(s) is (are) OFF. Watchdog has timed out and the device is in FailSafe mode. The outputs are as configured with the RFS resistor connected to FSI. RST and WAKE must be transitioned to logic [0] simultaneously to bring the device out of the FailSafe mode or momentarily tied the FSI terminal to ground.
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Fault
0 1 1 1
No
FailSafe
Yes
x = Don't care.
Sleep Mode
The default mode of the 33984 is the Sleep mode. This is the state of the device after first applying battery voltage (VPWR), prior to any I/O transitions. This is also the state of the device when the WAKE and RST are both logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal 5.0 V regulator, are off to minimize current draw. In addition, all SPI-configurable features of the device are as if set to logic [0]. The device will transition to the Normal or Fail-Safe operating modes based on the WAKE and RST inputs as defined in Table 11.
0 6.0 15 30
Fail-Safe Mode Disabled Both HS0 and HS1 OFF HS0 ON, HS1 OFF Both HS0 and HS1 ON
Normal Mode
The 33984 is in Normal mode when: * VPWR is within the normal voltage range. * RST terminal is logic [1]. * No fault has occurred.
The Fail-Safe mode can be detected by monitoring the WDTO bit D2 of the WD register. This bit is logic [1] when the device is in fail-safe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST terminals from logic [1] to logic [0] or forcing the FSI terminal to logic [0]. Table 11 summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI terminal is tied to GND, the Watchdog fail-safe operation is disabled. Loss of VDD If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The two outputs can still be driven by the direct inputs IN1:IN0. The 33984 uses the battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing fail-safe device operation with no VDD supplied. In this state, the watchdog, overvoltage, overtemperature, and overcurrent circuitry are fully operational with default values.
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Fault Mode
The 33984 indicates the following faults as they occur by driving the FS terminal to logic [0]: * * * * Overtemperature fault Open load fault Overcurrent fault (high and low) Overvoltage and undervoltage fault Open Load Fault (Non-Latching) The 33984 incorporates open load detection circuitry on each output. Output open load fault (OLF) is detected and reported as a fault condition when that output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled trough SPI (bit OL_dis). Overcurrent Fault (Latching) The device has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in Figure 4, page 13. The eight different overcurrent low detect levels (IOCL0 :IOCL7) are likewise illustrated in Figure 4. If the load current level ever reaches the selected overcurrent low detect level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the effected output OFF. If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCL driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again.
The FS terminal will automatically return to logic [1] when the fault condition is removed, except for Overcurrent and in some cases Undervoltage. Fault information is retained in the fault register and is available (and reset) via the SO terminal during the first valid SPI communication (refer to Table 9, page 20).
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Overtemperature Fault (Non-Latching) The 33984 incorporates overtemperature detection and shutdown circuitry in each output structure. Overtemperature detection is enabled when an output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset of the device. Overvoltage Fault (Non-Latching) The 33984 shuts down the output during an overvoltage fault (OVF) condition on the VPWR terminal. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit OD1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection and diagnostic can be disabled trough SPI (bit OV_dis). Undervoltage Shutdown (Latching or Non-Latching) The output latches OFF at some battery voltage between 5.0 V and 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. This ensures that when the battery level then returns above 6.0 V, the device can be returned to the state that it was in prior to the low VPWR excursion. Once the output latches OFF, the outputs must be turned OFF and ON again to re-enable them. In the case IN1:IN0 = 0, this fault is non-latched. The undervoltage protection and diagnostic can be disabled through SPI (bit UV_dis).
Reverse Battery
The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output's gates are enhanced to keep the junction temperature less than 150C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required.
Ground Disconnect Protection
In the event the 33984 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless the state of the output at the time of disconnection.
33984 22
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Soldering Information
The 33984 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 33984 was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows: * Convection: 225C +5.0/-0C * Vapor Phase Reflow (VPR): 215C to 219C * Infrared (IR)/Convection: 225C +5.0/-0C The maximum peak temperature during the soldering process should not exceed 230C. The time at maximum temperature should range from 10 s to 40 s maximum.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33984 23
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PACKAGE DIMENSIONS
PNA SUFFIX 16-TERMINAL PQFN NONLEADED PACKAGE CASE 1402-02 ISSUE B
12
12 1 2X
A M 0.1 C
PIN 1 INDEX AREA
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12
15
16
M PIN NUMBER REF. ONLY 0.1 C 2.2 2.20 2.0 1.95 0.05 C 4
B
2X
0.1 C
10X
0.6 0.2 0.1 0.05
DETAIL G
M M
0.05 0.00 DETAIL G
VIEW ROTATED 90 CLOCKWISE
C
SEATING PLANE
CAB C
9X
2X
0.95 0.55 0.1 0.05 1.1 0.6
M M
CAB C
1
0.9
2X 1.075
0.1 C A B 5.0 4.6
12
6X
6X
2.05 1.55
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. COPLANARITY APPLIES TO LEADS AND CORNER LEADS. 5. MINIMUM METAL GAP SHOULD BE 0.25MM.
2.5 2.1 1.45 5.5 4X 1.05 5.1 0.1 C A B
13
3.55 1.85
14
(2)
6X
0.8 0.4 1.28 0.88
(10X 0.25) 2.25 1.75 (2X 0.75)
16
15 2X
(10X 0.4) 0.1 C A B
(0.5) (10X 0.5) 10.7 10.3 0.1 C A B 11.2 10.8 0.1 C A B VIEW M-M
0.15 0.05
6 PLACES
33984 24
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
NOTES
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33984 25
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NOTES
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33984 26
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
NOTES
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33984 27
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